Most performance gaps in ML workloads come from operator implementations, not model architecture. Tile-lang treats operator authorship as a first-class engineering task: a compact, Pythonic DSL that surfaces tiling, pipelining, shared-memory and fragment primitives while compiling through a TVM-centered toolchain to multiple low-level backends. The result is a workflow that trades boilerplate kernel engineering for concise, tuneable kernels that can reach assembly-level performance on modern GPUs.
What Sets It Apart
- Low-level tiling primitives exposed as high-level constructs — so what? Teams can express block-level copy, shared-memory layout and pipelined loops without writing CUDA/assembly, reducing iteration time for microkernel experiments.
- Multi-backend codegen anchored on TVM — so what? The same DSL can target CUDA (including CuTeDSL/CUTLASS templates), NVRTC for faster compile cycles, WebGPU, Apple Metal and vendor IRs (e.g., Ascend), helping portability across HW without reauthoring kernels.
- Focused operator examples and benchmarks — so what? Ready examples (GEMM, dequantize GEMM, FlashAttention, MLA) and benchmark scripts let engineers validate performance against device-specific baselines quickly.
Who It's For
Great fit if you are an ML systems engineer or researcher implementing or tuning low-level operators for training or inference, need fine-grained control over tiling/layout/pipelining, and want a faster iteration loop than hand-writing CUDA/assembly. Look elsewhere if you only need high-level model APIs, prefer entirely auto-generated kernels without manual tiling control, or cannot invest time in backend/toolchain familiarity (TVM, device specifics).
Where It Fits
Tile-lang sits between high-level operator libraries (cuBLAS/cuDNN, fused operator libraries) and handwritten device assembly: it’s more explicit than a fully auto-scheduled compiler but far more productive than raw CUDA/ASM. Compared to Triton or raw TVM kernels, tile-lang emphasizes concise syntax for tile-level programming plus a suite of device-focused backends and examples aimed at ML operator workloads.
How It Works
Authors write kernels in a Python-like DSL; the compiler lowers those kernels into TVM IR and then into backend-specific codegen (CUDA/CuTeDSL, NVRTC, Metal, WebGPU, Ascend IR). The project includes debugging helpers (e.g., printing, layout plotting), nightly wheels, and example operator implementations that demonstrate tuning knobs and performance tradeoffs. Expect to pair tile-lang with device knowledge and benchmarking to unlock top-end performance.
